On the Influence of the Position-Dependence of Stress on Device Performance

Abstract

We investigate the effect of the position-dependence of stress on device simulation in a 65 nm node technology using mechanical simulations for the stress created by a nitride liner in the n-MOSFETs and by SiGe source/drain pockets in the p-MOSFETs. For gate lengths below 0.1 μm, the difference in the linear and especially the saturation drain current becomes negligible when either considering the position-dependence of stress or using a constant stress picked from the source-side of the channel. In contrast, significant differences in the current enhancements exist for different mobility models (linear piezoresistance versus Intel hole mobility model) and different transport equations (drift-diffusion versus hydrodynamic).