On the importance of the Vg,max– Vth parameter on LTPS TFT stressing behavior

Abstract

In this work we point out the importance of the device parameter V g,max– V th (the difference between the gate voltage at maximum transconductance and the threshold voltage obtained from linear extrapolation method) for LTPS TFTs under dc stress. The evolution of this parameter with stress time is monitored for the first time, along with the other typical device parameters ( V th, G m,max, S) in order to further clarify the nature of the traps generated. In the first dc stress case considered, we observed very different S degradation of the two samples, but very similar G m,max degradation, as well as similar V g,max– V th evolution. Therefore, G m,max evolution with stress time was found to be related more strongly to tail state generation, probed through V g,max– V th, and not to midgap trap generation, probed through S. In the second case, no midgap state generation is observed, but only severe tail state generation. Hence, the nature of the created defects and the reason for the significant G m,max reduction could only be probed through the observation of V g,max– V th, a parameter not utilized until now. Finally, stressing both n- and p-channel devices, we are able to explain the much more intense G m,max degradation observed for n-channel devices, associating it to the larger tail state generation in n-channel TFTs, also pointed by V g,max– V th evolution with stress.