On the Impact of Nanotopography of Silicon Wafers on Post-Chemical Mechanical Polished Oxide Layers

Abstract

The impact of nanotopography of silicon wafers on the thickness homogeneity of oxide layers after deposition and chemical mechanical polishing (CMP) is investigated. Comparison of nanotopographical height with post-CMP oxide thickness for the same position on a wafer may result in inconclusive data with no obvious correlation. However, a simple relation is obtained when (i) the root-mean-square (rms) roughness of nanotopographical height (ii) the standard deviation of post-CMP oxide thickness and (iii) the standard deviation of post-CMP oxide thickness caused only by fluctuations of the combination of oxide deposition and CMP are considered: α is a coefficient that is fairly independent of the nanotopography features of wafers as well as the area for which the rms roughness and the standard deviations are determined, but which depends on the planarization length of the CMP process applied. Regarding the CMP process used in the present investigation, α is found to be about indicating that only 15% of the nanotopographical height values of as-polished wafers transfer into post-CMP oxide thickness variations. A negative α implies that nanotopographical surface depressions are related to enhanced post-CMP oxide thickness and vice versa. © 2002 The Electrochemical Society. All rights reserved.