Abstract
In this paper, we consider the problem of hard-real-time (HRT) multiprocessor scheduling of embedded streaming applications modeled as acyclic dataflow graphs. Most of the hard-real-time scheduling theory for multiprocessor systems assumes independent periodic or sporadic tasks. Such a simple task model is not directly applicable to dataflow graphs, where nodes represent actors (i.e., tasks) and edges represent data-dependencies. The actors in such graphs have data-dependency constraints and do not necessarily conform to the periodic or sporadic task models. In this work, we prove that the actors in acyclic Cyclo-Static Dataflow (CSDF) graphs can be scheduled as periodic tasks. Moreover, we provide a framework for computing the periodic task parameters (i.e., period and start time) of each actor, and handling sporadic input streams. Furthermore, we define formally a class of CSDF graphs called matched input/output (I/O) rates graphs which represents more than 80 % of streaming applications. We prove that strictly periodic scheduling is capable of achieving the maximum achievable throughput of an application for matched I/O rates graphs. Therefore, hard-real-time schedulability analysis can be used to determine the minimum number of processors needed to schedule matched I/O rates applications while delivering the maximum achievable throughput. This can be of great use for system designers during the Design Space Exploration (DSE) phase.
Highlights
The ever-increasing complexity of embedded systems realized as Multi-Processor Systemson-Chips (MPSoCs) is imposing several challenges on systems designers [18]
We prove that strictly periodic scheduling is capable of delivering the maximum achievable throughput for matched I/O rates graphs
The objective of the experiment is to compare the throughput of streaming applications when scheduled using our strictly periodic scheduling to their maximum achievable throughput obtained via self-timed scheduling
Summary
The ever-increasing complexity of embedded systems realized as Multi-Processor Systemson-Chips (MPSoCs) is imposing several challenges on systems designers [18]. Model-of-Computation (MoC) based design has emerged as a de-facto solution to the first challenge [10]. In MoC-based design, the application can be modeled as a directed graph where nodes represent actors (i.e., tasks) and edges represent communication channels. Different MoCs define different rules and semantics on the computation and communication of the actors. In [5], the CSDF model is defined as a directed graph G = V , E , where V is a set of actors and E ⊆ V × V is a set of communication channels. The number of actors in a graph G is denoted by N = |V |. An acyclic graph G has a number of levels, denoted by L, which is given by Algorithm 1.
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