On-the-Field Test and Configuration Infrastructure for 2-D-Mesh NoCs in Shared-Memory Many-Core Architectures

Abstract

This paper addresses the important issue of fault tolerance in network-on-chip (NoC) and presents an on-the-field test and configuration infrastructure for a 2-D-mesh NoC, which can be used in many generic shared-memory many-core tiled architectures and MPSoCs. This paper also details all the hardware and software means needed to: 1) initialize the NoC in a clean state (self-deactivation of faulty NoC components using a controlled built-in self-test strategy) and 2) set up a distributed collaborative configuration infrastructure that can be used to make the chip autonomously determine, during its initialization, the operational degraded architecture, identify and bypass black holes. Experimental results prove that the approach is effective and lightweight in terms of additional software and hardware resources.