On the feasibility of superjunction thick-SOI power LDMOS transistors for RF base station applications

Abstract

The feasibility of applying the superjunction (SJ) concept to a thick-SOI LDMOS transistor for base station applications is studied in this paper. An extensive comparison with conventional RF LDMOS structures is performed in terms of breakdown voltage (VBR) versus drift resistance (Rdr) values. Unlike conventional LDMOS structures, the Rdr value in SJ LDMOS structures not only depends on the doping concentration but especially on the characteristics of P and N pillars. The charge compensation due to inter-diffusion between adjacent pillars is responsible for the observed Rdr increase. In order to accomplish an optimum pillar formation with the minimum possible transition between P and N pillars with inherent net doping reduction, high energy multi-implantations and a small thermal budget must be used. Moreover, the distance between P and N pillar implantation windows must be properly set to alleviate the doping inter-diffusion effect. The VBR/Rdr ratio value is a good indicator to evaluate the SJ LDMOS feasibility for RF applications.