On the Design of Power Attack Immune Spintronic Associative Memory

Abstract

The growing utilization of neural networks has led to a heightened focus on the hardware implementation of such networks. Security concerns associated with these implementations pose a significant challenge in this regard. Among these problems, the vulnerability of these networks against side-channel attacks such as power attacks can be mentioned. This paper presents a technique to enhance the resilience of hardware implementations of neural networks, particularly Hopfield neural networks, to mitigate the risks posed by power attacks. In addition to the fact that the proposed method makes it impossible to attack the network, it also reduces the power consumption of the entire circuit by reducing the leakage currents. The simulation results demonstrate that the proposed approach also achieves about a 10% reduction in energy consumption while concurrently improving the accuracy of the implemented associative memory by 1.1%.