On the design of optimal 2D filters for efficient hardware implementations of image processing algorithms by using power-of-two terms

Abstract

In this paper, we present a general approximation for 2D filters by using only power-of-two terms. This enables to easily implement these filters in electronic devices such as FPGA and ASIC just by using simple hardware shifters and adders/subtractors. Consequently, no division and no multiplication operators are required, which can reduce the memory and the power needed for computing operations such as convolution. Instead of using only additions and power-of-two terms for representing a number like in the standard binary decomposition, our model also uses subtractions for representing and approximating numbers. In addition, we propose a binary tree structure for computing a minimal representation in power-of-two terms in such a way that hardware shifters used for performing a convolution with a low-pass filter for example are well reduced to their minimum. Based on some experiments performed for contrast enhancement, which is a common image processing operation, we have noticed that good results can be obtained using our approximation in terms of image quality, hardware resources, and power consumption when compared to some other binary representations.