On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology

Adilson S Cardoso,Anup P Omprakash,Nedeljko Karaulac,Partha S Chakraborty,John D Cressler,Prabir Saha

doi:10.1109/s3s.2014.7028204

On the cryogenic performance of ultra-low-loss, wideband SPDT RF switches designed in a 180 nm SOI-CMOS technology

Adilson S Cardoso, Anup P Omprakash + Show 4 more

https://doi.org/10.1109/s3s.2014.7028204

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Publication Date: Oct 1, 2014

Citations: 1

Affiliation: Georgia Institute of Technology

#Single-pole Double-throw #RF Switches + Show 8 more

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Abstract

The RF cryogenic performance of ultra-low-loss, wideband (DC to 40 GHz) single-pole double-throw (SPDT) RF switches implemented in a 180 nm SOI CMOS technology is reported for the first time. Results show that the switch insertion loss (IL), isolation (ISO), small- and large-signal linearity all improve as the temperature decreases. DC characterization of individual transistors was performed and analyzed to provide insight into the mechanisms underlying the observed changes in the RF switches.

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