Abstract
The original method and route of functional-flow synthesis of ultra-large integrated circuits is considered. A way of reducing the degree of parallelism and the original algorithms is presented. When transferring the algorithm to the target platform, the imposed restrictions are taken into account. It is proposed to use the developed methods of formal verification to confirm the adequacy of the results of the transformation We mean to the transformation from the algorithms descried in the functional-flow parallel programming language to the hardware description languages.
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