Abstract
This paper addresses the issues pertaining to testing field programmable gate arrays (FPGAs) using an array-based technique. In particular, the issues of testing configurable devices (such as multiplexers and flip-flops) in the sequential array process (as the most significant factor for assessing complexity) and the arrangement for pipelining test vectors are treated in detail. Initially testing procedures for a configurable flip-flop and a programmable multiplexer are presented. At system-level, two new pipeline arrangements referred to as the quasi-pipeline and normal pipeline structures are proposed for reducing the number of programming phases. The application of the proposed approaches to the XC4000 FPGA family is also presented.
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