Abstract

High yield processing of advanced integrated devices poses stringent demands on substrate and active device layer quality. Wafers have to be free of electrically active defects and should therefore be free of so called large pit defects and Crystal Originated Particles (COP’s) which can be formed during Czochralski (Cz) crystal growth. These COP’s are surface pits formed by large vacancy clusters and are observed by surface inspection tools based on light scattering as “particles”. They are formed by vacancy clustering during crystal growth. In Cz Si these defects can also be observed inside the bulk of the material by using infra red light scattering tomography and transmission electron microscopy. Recently similar defects were observed on polished Cz Ge wafers using optical and scanning electron microscopy and the same surface inspection tools as used for silicon wafers. In the present paper the characterisation of grown-in voids in Si and Ge using these various techniques is discussed. The observed void size-density distributions are compared with results of the simulation of vacancy incorporation and clustering during the Czochralski growth process.

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