On the bit complexity of parallel computations

Abstract

The theoretical models of computation commonly used to design and analyze algorithms, whether sequential or parallel, usually assume that the word size is fixed and that the entire word is available at once. The purpose of this paper is to describe a number of architectures that are specifically designed to handle those situations where the conventional assumptions do not hold, i.e. where words can be arbitrarily long and/or their digits arrive serially. Four problems are considered: computing the sum of n k-bit integers, multiplying two k-bit integers, finding the partial sums of an array of n k-bit integers. Our solutions to these problems are all based on the concept of “on-the-fly” use of the input and intermediate result bits. For each architecture we present, the product of the solution time and the number of logical gates used is an improvement over that of any previously known circuit for the given problem that uses more than a constant number of processors.