Abstract
The paper presents an analytical model to determine memory band-width for a shared memory multiprocessor system where the processors and the memory modules are connected by the Hierarchical Interconnection Network (HIN). In our modelling technique, we decompose the memory references of a hierarchical system into as many groups as the number of hierarchical levels (e.g., local, nonlocal, and global levels). The contribution of each group of processors and memory references is determined separately for the bandwidth. Thus, out modelling technique involves a number of decomposed models rather than a single model for the entire system. The total bandwidth is determined by adding the contributions of all the bandwidth calculated from the decomposed model. The results are compared with the current research available in the literature.
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