On Testing of Superscalar Processors in Functional Mode for Delay Faults

Abstract

In-field test is becoming important due to reliability concerns arising from aggressive technology scaling coupled with variation in manufacturing process. In advanced technology nodes, increasing delay variation and decreasing delay tolerance makes the condition worse. Conventional scan based delay test environment can be different from the normal operation of a circuit and has drawbacks like area overhead, application of nonfunctional vectors, clock stretching etc. Therefore, an alternative functional mode test is needed. This paper attempts to integrate a functional test and structural test. It generates structural test under functional constraints and applies in the functional mode. In an out-of-order processor, instructions are not executed in program sequence. This feature poses challenge in application of delay test through software based self-test (SBST) technique. In this paper, we describe a SBST technique to test delay faults in computational blocks of an out-of-order superscalar processor without area overhead or timing penalty. The proposed technique is applied to superscalar processor implementing portable ISA (PISA). The experimental results show 99.12% delay test efficiency of computational blocks in an execution unit.