Abstract
In this paper a concept for the efficient design of a series of floating fractional-order elements (FOEs) is proposed. Using even single or a very limited number of so-called “seed” FOEs it is possible to obtain a wide set of new FOEs featuring fractional order being in the range , where n is an arbitrary integer number, and hence enables to overcome the lack of commercial unavailability of FOEs. The systematic design stems from the utilization of a general immittance converter (GIC), whereas the concept is further developed by proposing a general circuit structure of the GIC that employs operational transconductance amplifiers (OTAs) as active elements. To show the efficiency of the presented approach, the use of only up to two “seed” FOEs with a properly selected fractional order as passive elements results in the design of a series of 51 FOEs with different being in the range that may find their utilization in sensor applications and the design of analog signal processing blocks. Comprehensive analysis of the proposed GIC is given, whereas the effect of parasitic properties of the assumed active elements is determined and the optimization process described to improve the overall performance of the GIC. Using OTAs designed in 0.18 μm TSMC CMOS technology, Cadence Virtuoso post-layout simulation results of the GIC are presented that prove its operability, performance optimization, and robustness of the proposed design concept.
Highlights
We elaborate the efficient utilization of so called “seed” fractionalorder elements featuring fractional order αseed that are employed in a general immittance converter to design a series of fractional-order elements
Using operational transconductance amplifiers (OTAs) as active elements, we propose possible implementation of the general immittance converter and use it to design a wide series of floating fractional-order elements (FOEs)
Two “seed” FOEs are designed and further utilized in the proposed general immittance converter (GIC), whereas following the recommendations from Section 4.2, the optimization steps are verified to improve the overall performance of the GIC
Summary
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. We elaborate the efficient utilization of so called “seed” fractionalorder elements featuring fractional order αseed that are employed in a general immittance converter to design a series of fractional-order elements We partially presented this concept in [44], where the design of a series of grounded FOEs with fractional order [−2, 2] was presented. Using operational transconductance amplifiers (OTAs) as active elements, we propose possible implementation of the general immittance converter and use it to design a wide series of floating FOEs. In Section 4, the behavior of the proposed GIC is further analyzed.
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