On-state and off-state stress-induced degradation in unhydrogenated solid phase crystallized polysilicon thin film transistors

Abstract

The effects of DC bias gate and drain on-state and off-state stresses on unhydrogenated solid phase crystallized polysilicon thin film transistors were investigated. The observed, under gate bias stress, threshold voltage turnaround from an initial negative shift due to hole trapping to positive shift with logarithmic time dependence attributed to electron trapping was suppressed when a drain bias was added for a combined gate–drain on-state stress; this suppression was more effective for larger gate bias. The subthreshold swing, the midgap trap state density and the transconductance exhibited logarithmic degradation, in line with the positive V th shift. The stressing time needed for V th turnaround decreased, indicating increase of electron trapping, and the midgap trap state density increased in correlation with increasing stressing current I DS as stressing V DS increased, for a given on-state stressing V GS. Off-state gate–drain stressing resulted in logarithmic positive V th shift, after a small initial negative shift, and in reduction of the leakage current due to stress-induced shielding of the gate field. An applied inverse stress resulted in less severe V th degradation due to stress-induced effects being more concentrated near the source rather than the drain in that case.