On Proving Circuit Lower Bounds against the Polynomial-Time Hierarchy

Abstract

We consider the problem of proving circuit lower bounds against the polynomial-time hierarchy. We give both positive and negative results. For the positive side, for any fixed integer k>>0, we give an explicit $\Sigma^{\rm p}_2$ language, acceptable by a $\Sigma^{\rm p}_2$ machine with running time O(nk2+k ), that requires circuit size >nk. This provides a constructive version of an existence theorem of R. Kannan [Inform. and Control, 55 (1982), pp. 40--56]. Our main theorem is on the negative side. We give evidence that it is infeasible to give relativizable proofs that any single language in the polynomial-time hierarchy requires superpolynomial circuit size. Our proof techniques are based on the decision tree version of the Switching Lemma for constant depth circuits and the Nisan--Wigderson pseudorandom generator. We also take this opportunity to publish some previously unpublished older results of the first author on constant depth circuits, both straight lower bounds and inapproximability results based on decision tree--type Switching Lemmas.