Abstract
The paper shows the FPGA dedicated method of mapping a PLC program written according to the IEC61131-3 standard. There is described complete synthesis process from the program description to hardware implementation through mapping and scheduling procedures. PLCs’ programming languages are translated into common intermediate graph form. It enables massive parallel implementation. There is presented an originally developed graph structure with attribute edges. Finally the graph mapping methodologies are discussed. A general hardware mapping concept and algorithms for utilizing specific FPGA components are presented. An efficient mapping of the DSP48 block is shown. It attempts to utilize all features of the block in pipelined calculation model. The consideration are summarized with implementation result comparison for general hardware mapping and with use of DSP48 units.
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