On Multiplexed Signal Tracing for Post-Silicon Validation

Abstract

Trace-based debug techniques have widely been utilized in the industry to eliminate design errors escaped from pre-silicon verification. Existing solutions typically trace the same set of signals throughout each debug run, which is not quite effective for catching design errors. In this paper, we propose a multiplexed signal tracing strategy that is able to significantly increase debuggability of the circuit. That is, we divide the tracing procedure in each debug run into a few periods and trace different sets of signals in each period. We present a trace signal grouping algorithm to maximize the probability of catching the propagated evidences from design errors, considering the trace interconnection fabric design constraints. Moreover, we propose a trace signal selection solution to enhance the error detection capability. Experimental results on benchmark circuits demonstrate the effectiveness of the proposed solution.