Abstract
An on-line error-detectable high-speed multiplier is described. It is based on the multiplication algorithm which we have previously proposed. In the algorithm, the redundant binary representation each of whose digits is 0, 1, or -1 is used. The multiplier consists of an input encoder, a multiplication block, and an error checker. The input encoder encodes each primary input bit into the 1-out-of-2 code. The multiplication block is designed by means of the three-rail logic. The three-rail logic is a logic design technique in which three mutually exclusive conditions calculated in a circuit are encoded in 1-out-of-3 code and the circuit is designed to be inverter-free. The error checker is a totally self-checking two-rail checker and produces a bit pair as an error indicator. The multiplier can perform n-bit multiplication in a time proportional to log <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> n and has a regular cellular array structure suitable for VLSI implementation. Furthermore, we can detect any error caused by unidirectional stuck-at faults on gate output lines in normal operation by observing the error indicator. Many errors caused by other faults can be also detected. We can develop various on-line error-detectable high-speed arithmetic circuits using the redundant binary representation and the three-rail logic.
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