On high noise immunity CMOS design scheme with low leakage power consumption

Abstract

The noise immunity of modern CMOS digital design became an important metric as well as its power consumption. In this paper, we present a high reliability yet low power CMOS design scheme. The scheme is a combination of a dual threshold voltage technique (DVTCMOS) and a multiple threshold voltage technique (MTCMOS). The technique will be referred to as DVTMTCMOS. The simulation results show that the reliability of the scheme, in terms of logic error rate and delay error, is better than that of other low power design schemes such as dual supply voltage, MTCMOS or traditional digital design using one low threshold voltage. The results show also that the technique uses around 40% of sleep transistor size and consumes 70% active leakage power of MTCMOS and consumes around 0.001 standby leakage power of the DVTCMOS technique with very small degradation in circuit speed (1-3.4%). The testing circuits have been simulated using HSPICE assuming 0.18 /spl mu/m CMOS technology.