On Heavy Ion Induced Hard-Errors in Dielectric Structures

Abstract

Heavy ion induced failures in SiO2 and SiO2/Si3N4 composite capacitors were studied for ion linear energy transfers (LETs) from 15 to 85 MeV/(mg/cm2). Key findings of this study were the following: 1) hard errors are caused by a combination of energy deposited by the ion and from electrical conduction through the plasma channel formed by the ion strike, 2) there is an inverse linear relationship between ion energy deposition and the bias voltage required for composite device failure and 3) the angular dependence of the failure threshold voltage closely follows an inverse cosine relationship. Empirical equations are presented that allow the critical failure thresholds to be calculated from the ion LET for both silicon dioxide and metal-nitride-oxide-semiconductor (MNOS) composite devices. A failure model is proposed based on the energy deposition in the dielectric and rapid thermal diffusion of gate material through the dielectric.