Abstract
A floor-plan is a rectangle partitioned into a set of disjoint rectilinear polygonal regions (called modules). A floor-plan F represents a plane graph G as follows: Each vertex of G corresponds to a module of F and two vertices are adjacent in G iff their corresponding modules share a common boundary. Floor-plans find applications in VLSI chip design. If a module M is a union of k disjoint rectangles, M is called a k-rectangle module. It was shown in [K.-H. Yeap and M. Sarrafzadeh, SIAM J. Comput., 22 (1993), pp. 500--526] that every triangulated plane graph G has a floor-planusing 1-, 2-, and 3-rectangle modules. In this paper, we present a simple linear time algorithm that constructs a floor-plan for G using only 1- and 2-rectangle modules.
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