On device EPE: minimizing overlay, pattern placement, and pitch-walk, in presence of EUV stochastics and etch variations (Conference Presentation)

Abstract

EUV lithography and multi patterning introduce variability often referred to as EUV and Etch stochastics. These consume a large part of the EPE (Edge Placement Error) budget. To bring EPE to the necessary specifications, the industry needs to minimize the key EPE contributors of CD, Overlay, pattern placement, pitch-walk, and LER. The challenge is that these attributes are being gauged by different metrology technologies, thus just matching these different metrology techniques might consume the entire EPE budget. Hence, the industry has sought solutions presented in this work that are capable of measuring the above attributes of EPE from a single image. The study presented will then investigate weather measuring all of EPE on a scribe like target introduces a pitch dependent bias that could be rid of - if all of EPE was measured on device. The paper will show data from thousands of EUV vias over multi-patterned interconnects of a real device. Once established that measuring on device is not prone to pitch dependent bias. The work will compare measuring and correcting EPE at ADI - after develop inspection, to reduce the time to accuracy compared to known methods of measuring accuracy, only at AEI, after etch. An attempt is made to investigate weather after etch accuracy methods used today insert a litho to etch metrology driven bias. After walking the audience through an EPE metrology budget minimization flow based on real images and data, the paper will look for further opportunities to minimize EPE at the source, such as self-aligned processes, beyond litho, specifically discussing spacer uniformity, and etch slant control versus overlay.