Abstract
We present necessary and sufficient conditions that must be satisfied by an irredundant logical path in a combinational subcircuit of LUT-based FPGAs, i.e. a path that can, under some delay assignment, detennine the speed of the circuit. A one-to-one relationship between functionally sensitizable logical paths and irredundant logical paths is found. Thus, a path can be classified as irredundant (or redundant) without any timing infonnation, based exclusively on the user-defined LUT functions and interconnection structure. An example demonstrates the applicability and the importance of the presented results for the evaluation of delay fault testability.
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