Abstract
We present necessary and sufficient conditions that must be satisfied by an irredundant logical path in a combinational subcircuit of LUT-based FPGAs, i.e. a path that can, under some delay assignment, detennine the speed of the circuit. A one-to-one relationship between functionally sensitizable logical paths and irredundant logical paths is found. Thus, a path can be classified as irredundant (or redundant) without any timing infonnation, based exclusively on the user-defined LUT functions and interconnection structure. An example demonstrates the applicability and the importance of the presented results for the evaluation of delay fault testability.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
