On design of efficient square generator

Abstract

The product of two numbers A and B can be calculated from A/sup 2/ and B/sup 2/. The simplest way for evaluating the squares is the use of ROM look up tables. However the conventional ROM table approaches are limited only for small bit size applications due to the unmanageable increase of the ROM table size. A novel design of square generator using a folding approach is presented to reduce the ROM table size. Results show that the a ROM of (2/sup 12//spl times/24) can store the squares of 12 bit numbers in 9.96 ns and takes 35 mm/sup 2/, where 0.8 /spl mu/mn CMOS process is assumed. With the folding approach, a square generator of 40 bit numbers can be designed using the same ROM table with additional circuitry. The 40 bit square generator takes 12.27ns in delay and 36.45% in hardware overhead. With a two level nested structure, the same ROM table can be used to design a 103 bit square generator which takes 14.58 ns in delay and 3.11 times the area of (2/sup 12//spl times/24) ROM, i.e., 10.9 mm/sup 2/. The bit size can be increased with more levels of the nested structure. The results are promising and thus the proposed approach is well suitable for large bit size applications.