Abstract
This paper presents a method of test compaction for stuck-at faults in combinational circuits, that complements previously proposed methods and allows further reduction in test set size in a cost-effective way. A given test set is compacted by generating additional test vectors. Each test vector added allows the removal of two or more test vectors from the existing test set, thus reducing its size. Experimental results for benchmark circuits demonstrate the effectiveness of the method.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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