On Common–Base Avalanche Instabilities in SiGe HBTs

Abstract

This paper presents a detailed investigation of the key device-level factors that contribute to the bias-dependent features observed in common-base (CB) dc instability characteristics of advanced SiGe HBTs. Parameters that are relevant to CB avalanche instabilities are identified, extracted from measured data, and carefully analyzed to yield improved physical insight, a straightforward estimation methodology, and a practical approach to quantify and compare CB avalanche instabilities. The results presented support our simple theory and show that CB-instability characteristics are strongly correlated with the parasitic base and emitter resistances. The influence of weak quasi-pinch-in effects are shown to contribute additional complexity to the bias dependence of the CB-instability threshold. Measured data from several technology nodes, including next-generation (300-GHz) SiGe HBTs, are presented and compared. Experimental analysis comparing different device geometries and layouts shows that while device size plays an important role in CB avalanche instabilities across bias, these parameters are not sensitive to standard transistor layout variations. However, novel measurements on emitter-ring tetrode transistor structures demonstrate the influence of perimeter-to-area ratio on CB stability and highlight opportunities for novel transistor layouts to increase .