On‐chip readout circuit for nanomagnetic logic

Abstract

An interface for reading the output of nanomagnetic logic (NML) is indispensable in order for NML to interact with existing CMOS ICs. Two alternative designs readout interface circuit (RIC1 and RIC2) for NML RIC are proposed based on dual barriers magnetic tunnel junction (DBs-MTJ), which is composed of two fixed layers (with anti-parallel magnetisation state) and a common free layer. RIC1 utilises the same layer order of DB-MTJ to form an up–down structure, whereas RIC2 exploits the reversed layer order of DB-MTJ to form a left–right structure. They utilise the three-terminal approach to realise the self-reference readout scheme. The magnetisation state of the free layers in RIC1 and RIC2 are controlled by the fringing field from NML and biased by the designed on-chip clock field. The sensing circuits in RIC1 and RIC2 utilise dynamic current mode and pre-charge sense amplifier, respectively. The simulation results indicate that RIC1 and RIC2 can achieve comparable magnetoresistance values, and also realise the logical readout scheme by itself. The switching time in RIC1 is less than that in RIC2, whereas time delay for data transportation in RIC1 is more than that in RIC2. RIC2 is more amenable than RIC1 to the current fabrication process technology.