On-Chip Optical Channel Routing for Signal Loss Minimization

Abstract

To satisfy the performance requirement in modern very large-scale integration designs, on-chip optical integration is a potential and developing technology in delay and power consideration. After completing the placement of the used optical devices in an optical layer, an optical routing plane can be divided into a set of horizontal or vertical optical channels. Based on the exploration of different routing geometries in optical planar routing, optical signal loss including length loss, bend loss, and crossing loss can be treated as the penalty of a routing result in optical planar routing. In this paper, a new grid-based non-Manhattan routing model is first proposed to assign the possible routing paths for optical interconnects. Furthermore, given a set of two-pin optical nets inside an optical channel in our proposed grid-based routing model, based on the optimality-oriented swap pass in Yan’s hierarchical bubble sorting, an efficient channel router can be proposed to complete the connection of the given optical nets with minimizing the total signal loss on the given nets inside an optical channel. Compared with Condrat’s swap-based channel router, the experimental results show that our proposed channel router decreases 41.08% of the total bend loss, 13.17% of the worst signal loss, and 23.57% of the total signal loss under the same total crossing loss on the average for ten tested examples in reasonable CPU time. Besides that, the experimental results show that our proposed channel router reduces 8.2% of the total wire length, 51.40% of the total routing tracks, and 9.98% of the total routing area for ten tested examples in reasonable CPU time.