On chip implementation of an OCR algorithm for musical notation

Abstract

Many of the OCR (Optical Character Recognition) systems are software solutions, based on PC or network based services. Hardware or embedded types of OCR systems, implemented in scanners, suffer from poor algorithm flexibility. The reasons of this situation are the cost and the time needed to design flexible hardware based system. The purpose of this work is to develop a simple algorithm for a standalone embedded OCR system for musical notes, based on an ALTERA FPGA development board. An innovative approach is to link between the theoretical, "high level" algorithm development and the solution implementation (at "low level"), by use the TRIZ principles. Thus the Embedded MATLAB is used as the same tool for both tasks: the development of an algorithm to solve the problem and the implementation of this algorithm to an appropriate hardware platform. The algorithm is based on a features' extraction method. Each token (a musical note) is defined by a simple set of features: as height, width, number of vertical lines, black line length at different horizontal lines. The classification is done by using the Maximum Likelihood (ML) method with some modifications. Thus, the calculation of the well known correlation coefficient between the wordbook and the tested token is done so fewer multiply operations are needed. Also, for the vectors' normalization, instead of dividing by vectors' norm, a multiplication by an extracted feature (the distance between staff lines) is done and thus fewer divide operations are needed. The use of integers, everywhere is possible, reduces the algorithm's execution time. For a hardware implementation of the algorithm, a DE2-70 ALTERA FPGA development board was used, with the customized NIOS II, 32-bit CPU. Using a NIOS II based CPU and peripherals a flexible system was developed in a short time. After testing and tuning the algorithm, to reduce the development time, instead of manual rewriting the whole code in C, the embedded MATLAB Coder (EMLC) was used to deploy the algorithm to the target CPU, configured in the FPGA device. The results confirm our method. The algorithm is zoom independent and a 92%-95% of successful recognition was achieved. The algorithm's running on a 50 MHz Cyclone II FPGA with a small NIOS II CPU was 180 times faster than the running on a PC with a 2 GHz CPU.