On-chip high voltage charge pump in standard low voltage CMOS process

Abstract

An on-chip high voltage tolerant 4VDD charge pump with symmetrical architecture in a standard low voltage 1.8 V 0.18 µm CMOS process is presented. For a 250 kΩ load, circuit efficiency of the charge pump is approximately 71%. All the MOS transistors satisfy typical voltage stress related reliability requirements for standard low voltage CMOS devices.