On-chip embedding mechanisms for large sets of vectors for delay test

Abstract

On-chip embedding of deterministic patterns is used for built-in test-pattern generation of large sets of vector pairs for path delay fault testing. A hardware efficient two-phase synthesis procedure is proposed to synthesize the test-pattern generator. Acceptable test-cycle requirements are met using a recent method, which reduces the test embedding problem to that of embedding the first vector in each pair. The approach is generalized to implement a hardware efficient on-chip pattern generator to test the embedded cores of a system on chip. The hardware overhead of the proposed method is reduced at a controllable increase on the number of test cycles.