On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation

Abstract

Post-silicon validation is critical for exposing subtle design errors that have escaped to the silicon prototypes. Its effectiveness is conditioned by in-system application of a large volume of functionally-compliant stimuli. In this paper, we present a methodology to design constrained-random stimuli generators, which are placed on-chip and are configurable at design-time to generate in-system functionally-compliant stimuli subject to user-programmable constraints provided at validation time. Central to our method is a cube-based representation of constraints. These cubes are used as masks that force pseudo-random sequences to map onto functionally-compliant stimuli. To reduce the on-chip storage requirements, masks are compressed at design-time and expanded on-the-fly at validation time using decompression circuitry. Experimental results evaluate the impact of our method on the requirements for on-chip logic and memory resources.