On-Chip CMOS Self-Decoupling Battery Cell System for Security Protection

Abstract

This article presents an effective on-chip power analysis attack countermeasure based on a new CMOS self-decoupling battery cell system that uses a self-decoupling circuit. The self-decoupling circuit dynamically controls an on-chip virtual power supply point, $V_{\mathrm {ddv}}$ , that can be used to power security-sensitive modules. The circuit automatically decouples an on-chip CMOS battery cell from powering a sensitive module when its voltage level reaches a designed minimum threshold level $V_{\mathrm {dd-min}}$ and connects it for a very short charging cycle to the chip’s main voltage supply, $V_{\mathrm {dd}}$ . The charging cycles for the experiments presented in this article are less than 10 ns and are designed to support the CMOS battery cell size and the minimum designed threshold voltage level $V_{\mathrm {dd-min}}$ . Simulation results of test designs implemented in the 45-nm CMOS technology process show that the proposed countermeasure is efficient when used with battery cell sizes that can power the protected cryptographic module for more than ten data operation cycles before recharging. In addition, using the on-chip self-decoupling battery cell system allows for power consumption savings within the protected module of up to 43 % due to the dynamic voltage scaling generated at the virtual power supply point.