On-chip characterization of interconnect parameters and time delay in 0.18 μm CMOS technology for ULSI circuit applications

Abstract

A real time, on-chip characterization technique is presented for extracting the interconnect parameters and for determining the associated time delays for ULSI circuit applications. To demonstrate the method, test chips were fabricated in both 0.25 and 0.18 /spl mu/m CMOS technologies, using state of the art process technologies. Results obtained in these two cases are compared and the changing trends and issues for interconnect parameters in making the transition from the 0.25 /spl mu/m to the 0.18 /spl mu/m technologies are discussed. A completed look-up table in conjunction with a working analytic expression of the time delay enables accurate modeling and optimization of interconnect parameters and time delays for a given specification of chip performance.