Abstract
Abstract In this paper we provide experimental evidence that digital VLSI circuit designs using an earlier proposed DFT method called segmented scan may be testable using fewer tests than needed for unsegmented scan versions of the same designs. Results on ISCAS 89 benchmark circuits show that the test set sizes for detecting stuck-at faults in segmented scan designs may be lower than the lower bounds on test set sizes for unsegmented scan versions. Thus, segmented scan design may be a way to achieve minimal test set sizes for digital VLSI circuits.
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