On Achieving Maximum Performance in Time-Varying Arrays

Abstract

Several important computationally intensive algorithms can be implemented on special purpose VLSI arrays. A number of such algorithms naturally map onto either heterogenous arrays or arrays employing PEs with switchable functions, or both. In many cases, such designs are the only known ones for VLSI implementation. Synchronization is generally achieved by assuming that the time required to perform basic PE computations is uniform, although the PEs perform different functions and may change their functions at different algorithmic steps. This simplistic approach may result in significant performance degradation. This paper addresses the properties, performance, and theory of time-varying heterogeneous arrays for the objective of achieving maximum performance. A systematic method for collision avoidance is formally introduced and analyzed. Our approach is based on dynamically balancing a two-level pipelined array through the use of a set of buffers. Another set of buffers is used to guarantee data synchronization. We show that if the initial delays (PE execution times) and the time variances are deterministic, an equivalent time-invariant array can be constructed (in polynomial time) which is optimal in speed. We describe a method for estimating the upper bound on computational time when array time variance is nondeterministic. Our method requires only knowledge of the bounds on initial delays.