On a Novel Dynamic Parallel Hardware Architecture for Lifting-Based DWT

Abstract

A novel fast scheme for Discrete Wavelet Transform (DWT) was introduced in last years under the name of lifting scheme [4, 7]. This new scheme presents many advantages over the convolution-based approach [3, 7]. For instance it is very suitable for parallelization. In this paper we present two new parallel FPGA-based implementations of the lifting-based DWT scheme. The first implementation uses pipelining, parallel processing and data reuse to increase the speed up of the algorithm. In the second architecture a controller is introduced to dynamically deploy a suitable number of clones accordingly to the available hardware resources on a targeted environment. These two architectures are able of processing large size incoming images or multi-framed images in real-time. The simulations driven on a Xilinx Virtex-5 FPGA environment has proven the practical efficiency of our contribution: the first architecture has given an operating frequency of 289 MHz, and the second demonstrated the controller's capabilities of deploying the maximum number of clones from the available resources, over a targeted FPGA environment and processing the task in parallel.