OFF-state degradation and correlated gate dielectric breakdown in high voltage drain extended transistors: A review

Abstract

High voltage transistors exhibit unique degradation modes that cannot always be explained based on classical degradation mechanisms. In this paper, we use the specific example of OFF-state degradation in high voltage drain extended transistors to develop a generalized degradation model that can be extended to a wide range of device geometries (DeMOS, LDMOS, CMOS) and bias conditions (OFF-state, sub-threshold, ON-state). We show that hot carriers generated from impact ionization of leakage current components are responsible for OFF-state degradation by breaking interfacial and bulk SiO bonds. The resultant degradation is shown to be universal and the kinetics of SiO bond breaking is explained based on a bond-dispersion model. The generalized “bottom-up” model also explains the correlated gate dielectric breakdown and higher Weibull slopes at OFF-state conditions which are not anticipated based on classical hot carrier models. Our approach unifies hot carrier degradation results from various laboratories across the world within a common conceptual framework.