Abstract
A bit-line sense amplifier (S/A) realizing a high sensitivity is essential for high-density DRAMs, because it is difficult to store enough signal charge within a smaller memory cell area. However, the sensitivity of the S/A tends to be degraded by an increase of the electrical imbalance between pair transistors in scaled-down dimension. A new bit-line sensing scheme realizing a high sensitivity was proposed. The proposed offset compensating bit-line sensing (OCS) scheme is effectively applicable to ULSI DRAMs where many transistors with a scaled-down dimension should be utilized. >
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