Off-Chip Memory Access Optimizations

Abstract

Due to the widening gap between processor and memory speeds, the memory interface has become a serious performance bottleneck because off-chip memory access is a relatively slow operation, incurring 10–20 times the delay of a typical datapath operation [PH94]. The consideration of memory issues is critical because, in many applications such as signal processing, memory storage dominates chip area and power — typical on-chip memory area is reported to be almost 10 times the typical area of a complex datapath [BCM95]. Thus, it becomes imperative to consider the effects of memory accesses during synthesis in order to realize efficient system designs. In this chapter, we address performance and power optimization issues in the interface between the synthesized hardware and off-chip memory blocks of the embedded system architecture, which are highlighted in Figure 3.1. In Section 3.1 we describe presynthesis transformations and optimizations that allow high-level synthesis (HLS) to effectively utilize contemporary off-chip memory modules such as DRAMs. In Section 3.2 we describe techniques to minimize address bus transition activity with the goal of reducing power dissipation during off-chip memory accesses.