Observation and Circuit Application of Negative Differential Conductance in Silicon Single-Electron Transistors

Abstract

A conductance anomaly displaying large negative differential conductance (NDC) has been observed in a drain current vs. drain voltage curve of Si single-electron transistors (SETs) at 27 K. The NDC appears, mainly in the single-electron-tunneling regime, in such a way that it aligns parallel to the edges of Coulomb diamonds, strongly suggesting that it reflects the discrete nature of the dot states. We show that high-gain SETs, i.e., SETs with gate capacitance that is well larger than the junction capacitances, enable us to regulate the appearance of NDC and to accentuate the tunneling conditions only at the drain side because of the asymmetric sharing of the source-drain voltage between the two junctions. We also show, using high-gain SETs, that the NDC results in a hysteresis loop of drain output voltage as a function of gate voltage for a constant drain-current bias. This enables us to use the SET as a Schmitt-trigger with excellent noise immunity.