Abstract

Combined input-crosspoint buffered (CICB) packet switches with dedicated crosspoint buffers require a minimum amount of memory in the buffered crossbar of N2 ldr k ldr L bytes, where N is the number of ports and k is the crosspoint buffer size, which is defined by the distance between the line cards and the buffered crossbar, and L is the cell (packet) size in bytes, to avoid buffer underflow under high-speed data flows. To support P traffic classes with different priorities, CICB switches requires N2 ldrkldrLldrP bytes to avoid blocking of high priority cells. In this paper, we study a shared-memory crosspoint buffered packet switch that uses small crosspoint buffers and no speedup to support differentiated services and long distances between the line cards and the buffered crossbar in practical implementations. The proposed switch requires 1/m of memory amount in a CICB switch to achieve similar throughput performance.

Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.