Numerical Optimization of Silicon Stacked Module for 3-D Packaging Applications

Abstract

Three-dimensional package format has gained more popularity for various applications because of the trend toward higher functional integration, miniaturization, and better electrical performance. This paper presents a design optimization study of a 3-D package using a silicon interposer. The package consists of three stacks with five dies. Electrical connections through the silicon interposers are done by through-silicone vias (TSVs) filled with electroplated copper. Initially, structural optimization of the package is conducted by a 2-D finite element analysis and later, statistical analysis is performed to estimate the coupled effects of parameters considered for the design. Carrier thickness variation is found to be the most significant effect on the package warpage. Interfacial stress between the copper plug and the silicon via hole has been investigated and reported. A 3-D model is constructed for the solder joint reliability study with SnAgCu material properties. Solder joint life with variation of parameters (i.e., board level underfill, higher standoff solder interconnect, and low CTE board) is studied, and all results are reported accordingly.