Numerical and experimental investigation of board level reliability of TEFCBGA

Abstract

As far as components with flip chip interconnects are concerned, one of the popular packaging solutions available in the market is thermally enhanced flip chip ball grid array (TEFCBGA) packages, which target mid to high performance applications. Traditional as it may be, the development of a reliable TEFCBGA package is still a very challenging task. The demands for high electrical performance with greater signal trace density, while constrained by fine core via manufacturing process, have been a driving factor of the reduction in core thickness of high density build up (HDBU) substrate as a flip chip carrier. The thin core substrate not only increases the package warpage, which will inevitably create additional downstream assembly problems during surface mount process, but degrades the significance of the role the substrate is playing as an effective buffer between the silicon die and the printed circuit board (PCB). To make things worse, the presence of an extra large Cu/low-k die on the HDBU substrate induces, in addition to potential serious coplanarity and board level reliability issues, high stresses in the die itself, which increase the risk of delamination at inter-layer dielectric (ILD) interfaces or even die cracking. No stones concerning package reliability can be left unturned during development phase of a TEFCBGA package in order to ensure that the flip chip packaging process is robust with high yield and compliance to JEDEC specifications. The focus of this paper, however, is on the board level reliability aspect of an extra large TEFCBGA package with body size of 50?50 mm?mm under accelerated thermal cycling (ATC) test. Finite element analysis (FEA) was used to evaluate its sensitivity to the change of design, material and process variables. Experiments were carried out to validate the predictions made by FEA simulation for similar packages. It was found that they were in good agreement and the model can be extended to study the effect of a wider range of variables on the board level reliability of a TEFCBGA package.