Numerical and experimental analysis of 500-V power DMOSFET with an atomic-lattice layout

Abstract

The authors analyze, numerically and experimentally, a new cell design, referred to as atomic-lattice layout (ALL). The polysilicon is patterned to form circular islands with narrow polysilicon bridges between them. This cell results in the formation of a p-n junction with a reverse curvature (the junction is concave, instead of convex, with reference to the top Si surface). This design allows a substantial reduction in the electric field strength in the active area of the device, thus permitting a significant improvement in the breakdown voltage (beyond that for the cylindrical junction). Modeling results showed that the drift-region doping concentration for the ALL design is much higher than that in the circular design. This is due to the reverse curvature effect in the ALL structure. However, the specific on-resistance of ALL DMOSFETs is not smaller than that of HEX DMOSFETs. This is a result of a larger JFET resistance in the ALL design as a result of current crowding under the poly islands. Devices of DMOSFETs with various cell sizes of ALL and HEX designs have been fabricated. Experimental results verified the theoretical predictions: the specific on-resistance of the ALL DMOSFET is similar to that of the HEX DMOSFET (77 m Omega -cm/sup 2/) but the Miller capacitance of the ALL design is two times smaller than that of the HEX design.