Abstract
In this work, we aim at highlighting the immunity of the junctionless Gate All Around (JLGAA) MOSFET against the induced interface tarps degradation at nanoscale level. In this context, a numerical investigation has been proposed to study the subthreshold behavior of the (JLGAA) MOSFET for ultra-low power applications. Based on 2-D numerical investigation, a small-signal parameters model for nanoscale JLGAA MOSFETs, including the hot-carrier induced interface charge effects, is developed. The numerical analysis has been used to simulate the transconductance and output-conductance in subthreshold region and to compare the performance of the investigated design and conventional GAA MOSFET, where the hot-carrier effects are included. High reliability, low fabrication cost and integration ability make JLGAA MOSFET promising candidate to improve the device reliability for the ultra-low power applications.
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