Nullcline-Based Design of a Silicon Neuron

Abstract

In this paper, we describe the design of a silicon neuron that exhibits type-I neural excitability, i.e., the frequency of spiking of the neuron approaches arbitrarily close to zero as the input current is reduced. Our design creates a conductance-based silicon model that can exhibit a saddle-node bifurcation. We present simulations and measured data from circuits fabricated in 0.35-μm CMOS that demonstrate both saddle-node bifurcation on invariant circle and saddle-homoclinic bifurcation. In our design, concepts from nonlinear dynamics are used not only for the analysis but also for the synthesis of the circuit. This leads to a nullcline-based methodology that enables a strategic approach for biasing the circuit in the desired regime in parameter space. Combined with the ability to set local biases (e.g., floating gates), this methodology should largely minimize mismatch in arrays of silicon neurons of this kind. The presented circuit is the most power efficient design reported so far, and we hope to fabricate larger arrays of this neuron to explore network behavior.